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Modern transceiver design for RFIC based applications2019-02-07T18:44:45+00:00

Modern transceiver design for RFIC based applications


There are several popular topologies being used for transceiver design. Super heterodyne topology is widely used, mostly for discrete transceiver design. It is not implemented in RFIC since it requires high Q IF filters to reject image interference and to improve the selectivity of the transceiver. When image frequency becomes zero, as for direct conversion topology, the high Q IF filter is replaced with simple LPF. This LPF can be easily integrated into the RFIC.
Direct conversion transceiver design or any other transceiver design, includes two major design considerations:

  1. The in-band performance of both transmitter and receiver channels for optimum SNR. The requirements for the SNR are based on the modulation schema and modem abilities. For example, HD video application and human voice application has different SNR requirement to maintain satisfied quality.
  2. The out-band performance. Defines the transmitter leakage to adjacent channel – ACPR (Adjacent Channel Power Rejection) and the receiver ability to reject interference while receiving wanted signal This consideration determines the mutuality of the transceiver in our crowded spectrum environment.

This tutorial analyzes the direct conversion topology of the receiver and transmitter channels, calculates ultimate in-band SNR, present ways to improve the SNR by circuit’s calibrations and other design techniques. This tutorial also analyzes the parameters that influence the transmitter ACPR, describes the mask requirement, analyze interferences and ways to improve the design of the receiver to handle crowded frequency spectrum including working in near far scenario.

Direct conversion transmitter

Transmitter and receiver design for direct conversion topology requires IQ modulator or demodulator. The BB signal frequency is centered to zero thus it needs orthogonal structure so the modem can evaluate the BB signals as complex format.
The transmitter includes three major blocks (See figure 1):

  1. I&Q DAC – usually located inside digital ASIC. The DAC’s output is current according to the digital word representing the signal coming from the modem. High accuracy resistors are used to convert the output current to voltage.
  2. RFIC – The major block in the transmitter. It includes integrated: LPF to reject the aliasing coming from the DAC, IQ modulator, synthesizer that generate LO signal to up convert the BB signals to RF and amplifiers for medium output power.
  3. FE – includes: PA for high output power and LPF to reject 2nd harmonics.


1. Direct conversion transmitter path.

 The signals can be represented as follows:12

Alternately, we can present the signals for single BB tone (Wm) using the equations below.


At I DAC output

4   At Q DAC output

5   At mixer I output

6  At mixer Q output

7  At RFIC output

Transmitter in-band SNR

Transmitter in-band SNR is required by the modem to assure BER or other quality factor, for reliable transmission. Different applications need different SNR from the RF section.
There are five major contributions for total SNR:
1. Quantization noise from DAC – The finite resolution of the DAC rise to a theoretical limitation to the SNR which is a function of the number of bits. It should be noted that the RMS quantization noise generally approximates broadband noise across the Nyquist BW. It is possible to eliminate the influence of the DAC quantization noise by choosing DAC with high sampling frequency and number of bits. It is common practice to design the quantization noise of the DAC for 10dB better the total required SNR.
For a full scale sine wave it can be shown that the theoretical RMS signal to quantization noise is given by:


  Where N=number of bits.

Note that SNR of the DAC is also the function of signal BW according to the following formula:


Where F sample is the DAC’s sampling frequency and F max is the maximum frequency of the sampled signal.

2. Phase noise is an undesired phase modulation of a signal caused mainly by the loaded Q of the VCO which is the major phase noise contributed block in the synthesizer. There are many other contributions for the integrated phase noise of the LO signal within the synthesizer but it is not the scope of this tutorial to analyze the synthesizer’s phase noise contributors. Common practice is to design the integrated phase noise for 3-4dB better then system required SNR.
There are several ways to reduce the phase noise of the synthesizer. Some of the effort concentrates in optimization of closed loop performance of the synthesizer but generally the VCO phase noise limits the total phase noise performance.
The VCO phase noise model can be describe according to Leeson’s equation below:


LPM – Single sideband phase noise density (dBc/Hz)
F – Device noise factor at operating power level A.
k – Boltzmann constant. ()
T – Temperature (K)
A – Oscillator output power (Watt)
QL – loaded Q
f0 – Oscillator frequency
fm – Frequency offset from the carrier.

3. IQ imbalanced – Ideally, it can be seen from equation (7) that the output signal from IQ modulator is only on single sideband of the LO in the positive or negative direction depending on the sign of the multiplying complex exponential. However, in practical analog electronics, the gains and phase responses of the I&Q signal processing branches will never be exactly the same. This causes the frequency translation to take place in both directions. The sideband suppression is shown in the following formula:


Where G is the gain delta between I&Q and is the phase different between I&Q.
One way to overcome this problem is by calibration the IQ imbalanced using internal detector as it shown in figure 2.


Fig. 2. IQ imbalanced calibration schema.

The detector output is 1xIF which response to LO leakage of the signal and 2xIF which response to the IQ imbalanced. This output voltage is sampled by the modem. IQ imbalanced algorithm changes the IQ signal’s phase and amplitude to reduce the voltage of 2xIF signal. The IQ imbalanced calibration timing is determined according to the SNR performance needed. Common practice design and layout can achieve 30dB sideband suppression without the need of calibration. If calibration is done only in production phase, then the sideband suppression can improve by 5-10dB. Application that need better performance then 35dB needs to calibrate IQ imbalanced more frequently. Sideband suppression can be reduced by even 60dB after calibration. Note that the calibration should be done over base-band BW and over the entire RF frequency band.

4. Thermal noise – The amount of noise added to the transmission signal by active components along the RF path determine this SNR segment. Generally Thermal noise will not limit the total SNR performance of the transmitter but still the design of the transmitter should take it into consideration. The output SNR is a function of the transmitter noise figure according to the formula below:


Where, NF is the transmitter NF.

5. Non-Linearity of the transmitter path is the most critical parameter that determines the total SNR. The high linearity of the last stage together with high efficiency makes the design of this block very challenging. Those parameters determine the output power of the transmitter i.e. link distance, and power dissipation which is very critical factor for commercial market.
The SNR contribution by the linearity can be calculated simply with two tone IP3 measurement setup. The formula of the SNR is as follows:


The CF is a factor of the signal modulation. See figure below for the CF vs. number of tones in OFDM. The continues line represent the CF for in-band noise.


Fig. 3. CF vs. number of tones for OFDM.

According to the graph, the CF for OFDM with 64 tones is 13dB.

The efficiency of the PA is very important factor in the design phase. Therefore many PA’s in the market uses class AB topology. The PA works with DC operating point that find the balance between SNR performance and efficiency. Usually, this point is set for maximum output power as required from the application or regulation. See figure 4 for the EVM of power amplifier vs. output power.


Fig. 4. Power amplifier Pout

Note that the EVM for minimum output power is constant. When output power increases, the EVM decreases up to a point where the EVM collapse.
Overall in-band SNR of the transmitter can be calculated according to the following formula (14):


Transmitter ACPR

The transmitter ACPR describes the amount of leakage that causes interference from our transmission signal to adjacent channel. Regulation authorities define transmission mask to limit the power out-band. As shown in figure 5:


Fig. 5 Transmission mask for WLAN according to FCC.

The analysis of the transmission mask above includes four points in which, each point is the outcome of the performance of the different part of the transmitter.
The four points of the transmitter mask are as follows:

1. LO leakage near Fc – The direct conversion transmitter has LO signal which is at the same frequency as the transmitting signal. There is no possibility to filter the LO leakage and prevent it from leaking out. The LO leakage is generated by three mechanism: DC offset in the BB signals that multiple by LO signal, conducted LO leakage from the mixers to the RF path and radiated LO leakage from VCO to RFIC output. The third mechanism can be reduced if the VCO will operate at double frequency of the signal.
The RFIC’s LO leakage can be calibrated using the same circuit of IQ imbalanced calibration, but instead of detecting the 2xIF signal, it should detect the 1xIF signal.
This signal is the intermode between transmission BB sine wave and LO leakage. The modem tunes the DC offset between BB signals until the 1xIF intermode voltage is minimum according to the following fig:


Fig. 6. LO leakage calibration

2. 11MHz – This point is the outcome of the digital filters of the BB signal in the modem. The modem generates IQ signals according to the modulation schema. Then the digital ASIC shape the signals with shaping filter to limits the BW of the signal.
3. 20MHz – This point reflects the Non-linearity of the RF path. If the design is optimize for best linearity performance then this point is dominated by the power amplifier.
The side-lobs can be calculated from two tones IP3 measurement setup, as we saw in section III (5) but here the CF will be only 6dB according to the formula below:


4. 30MHz – This point and beyond it, reflects the noise floor of the transmitter. The NF determine the thermal noise power at the output of the transmitter according to the following formula:


K – Boltzmann constant.
T – Temperature (K)
F – Noise factor of the transmitter.
G – Gain of the transmitter.

Direct conversion receiver

The receiver includes three major blocks (See figure 7):
1. FE – includes BPF for out-band interference rejection from other application at different frequency bands.
2. RFIC – The major block in the receiver. It includes integrated: LNA, IQ demodulator, synthesizer that generates LO to convert RF signal to BB IQ signal, LPF for receiver selectivity/aliasing rejection and BB amplifiers to improve receiver dynamic range.
3. ADC – Sample IQ signal. Usually integrated in the digital BB ASIC.


Fig. 7.  Direct conversion receiver path.

The signals can be represented by single BB tone Wm using the equations below.

24  At RFIC input

25  At mixer  I   output

26  mixer  Q output

27  At I ADC output

28  At Q DAC output

Receiver in-band SNR

Receiver in-band SNR is required by the modem to assure BER or other quality factor, for reliable transmission. Different applications need different SNR from the RF section.
There are five major contributions for total SNR:

1. Quantization noise of ADC – Further to what was described on the quantization noise of the DAC, various error sources in the ADC cause the measurement SNR to be less then the theoretical value, 6.02N+1.76dB. These errors occur due to integral and differential nonlinearities, missing codes and internal ADC noise sources. In addition, the errors typically are a function of input slew rate and therefore increases as the input frequency gets higher. This is referred to SNR + distortion or S/ (N+D).

2. Phase noise – Similar behavioral for the transmitter and receiver but, the influence weight of the phase noise for the total SNR in the receiver is significant larger then transmitter. The phase noise is the major contribution for the SNR while, in the transmitter generally, the Non-linearity is the major contributor. In the receiver the target for the phase noise should be 1-2dB above the target for the total SNR.
There are several ways to minimize the phase noise of the synthesizer. The design of the synthesizer should be optimal to the functional performance of the system. The locking time and resolution are the major parameters that can be relaxed to get better phase noise of the synthesizer.
If needed the design of the synthesizer blocks can target low phase noise. It is very challenging and can determine the silicon process needed to support such high demand for phase noise. For example, the width of the top metal in design process that is used for the VCO inductor will influence on the phase noise of the VCO.
The VCO is the major contributor to the integrated phase noise of the synthesizer since in close loop operation it contributes phase noise far from the carrier. The modem can not use the training sequence to learn on the phase offset within the packet because it changes faster then the length of packet. If we choose to work with short packets, we can cancel more phase noise from the VCO but the throughput will be damaged.

3. IQ imbalanced – Similar to the transmitter, the receiver suffers from gain and phase imbalanced between channel I and channel Q. This gain and phase imbalances are also the factor of the I&Q channels gain setting. It makes this problem more critical from the transmitter because the transmitter gain setting is almost constant where the receiver change gains every packet. In that case it is obvious that if we need good IQ imbalance performance, we need to calibrate the receiver every packet. This conclusion will make our system to be very complicated. There are systems that use as part of the preamble time slot for IQ imbalanced calibration in the beginning of the packet. Other does only production calibration. Production calibration can get to 35dB IQ imbalanced. If the system need more that that, there are two ways to do it. One way is to transmit training sequence from calibrated transmitter to the receiver. Another way is to use the transmitter chain inside the RFIC for the calibration as describes in the figure below:


Fig. 8. RX IQ imbalanced calibration mechanism.

This method requires two steps: the first step is the calibration of the transmitter using the detector as describes in section IV. The next step is to use the calibrated transmitter to transmit sine wave and then to calibrate the receiver.

4. Thermal noise – Is the most critical parameter that determines the sensitivity of the receiver according to the following formula (22):


BW – Signal RF band-width.
NF – noise figure of the receiver chain.
SNR – required signal to noise ratio from the modem.

There is no difference in the sensitivity formula between different types of receiver’s topologies. Generally, good design will use low NF and high gain front-end to minimize the total NF of the receiver. This will come in contrary to the linearity of the receiver

5. Linearity – The linearity defines the upper limit of the receiver dynamic range, where the thermal noise defines the lower boundary. The received signal should be between those limits to assure required SNR. If the received signal will be strong (the distance between the transmitter and the receiver is short), the non-linearity effects will cause degradation in SNR. We can show as we did for the transmitter that with two tones IP3 measurement setup, we can calculate the SNR reduction due to non-linearity according to the formula below:


Where CF equals 13dB for OFDM with 64 sub carriers.
The mechanism that keeps the received signal within the dynamic range called AGC (Automatic gain control). This mechanism tuned the gain of the receiver according to the power of the received signal. Generally, there are two blocks in the receiver chain that can be tuned: LNA and VGA. See figure 9.


Fig. 9. SNR Vs. Input power for the receiver.

The graph shows the total SNR of the receiver which includes all the components of the SNR described above. When the input signal to the receiver is very low, the SNR of the receiver is dominant by the thermal noise. This section located on the left of the sensitivity level. When the input signal cross the sensitivity point, the thermal noise is no longer the major contribution to the SNR. The SNR in this section is dominated by all SNR contributors. The LNA is set to the maximum gain for minimum NF. When the received signal gets stronger, the linearity of the receiver is more dominated then thermal noise and the SNR starts to degrade. At this point the AGC mechanism reduce the gain of the LNA to middle so the front-end will have enough gain to deal with thermal noise and still have good linearity performance. When the input signal cross the maximum input power the linearity of the receiver is the dominate contributor to the total SNR.
The division of the gain in the receiver path is very critical to obtain high dynamic range. Generally, the gain in the front-end is around 30dB with 3-4 gain steps. The rest of the gain is implemented in the back-end with higher resolution.
Direct conversion receiver has many advantages, it is very simple to implement on silicon since it does not need selective BPF for image rejection. Still this type of topology has also many disadvantages. One of the major problems is the DC offset of the receiver. The received signal is down convert to BB near the DC. The DC must be block so it will not saturate the receiver back-end. If the blocking is done with very low pole HPF then the information is not damage but the step response of the filter is slow. Fast response receiver is very important for the AGC period. On the other hand, if the HPF will have fast response and far pole then the information will be damaged.